1. Field of the Invention
The present invention provides a method of automatically defining a landing via of a semiconductor wafer.
2. Description of the Prior Art
A dynamic random access memory (DRAM) is forme by numerous single transistors or otherwise known as DRAM memory cells. Each memory cell is composed of a metal oxide semiconductor (MOS) transistor and a capacitor connected in series. The design theory of DRAM involves the use of the MOS transistor as a switch for controlling a bit line so as to read data stored in the capacitor. A word line electrically connects with a source/drain of the transistor by first filling conductive materials in a bit contact hole. The conductive material filling in a node contact hole is used as an electrical connecting line to connect the underground electrode of a capacitor and a source/drain of a transistor.
The prior method of forming contact holes commonly uses high etching selectivity to perform a self-aligned contact etching. Both a landing pad and another contact plug are simultaneously formed in the bottom of an electrode contact to both reduce the difficulty of the electrode contact process and to increase the mis-alignment tolerance of the etching process so as to ensure the electrical properties of the entire DRAM.
However, as the size of semiconductor devices decreases, the aperture of contact holes also decreases correspondingly. Thus, it becomes increasingly difficult to form the electrode contact using only lithographic and etching processes. Modification of process will ensure yield, but does not solve the complicated steps involved in the self-aligned etching process. Therefore, an important factor in current semiconductor processes is the ability to simplify the method of fabricating contact holes in accordance with the increasing integration of semiconductor devices.
Please refer to FIG. 1 to FIG. 5. FIG. 1 to FIG. 5 are schematic diagrams for a prior art method of forming a landing pad 29. The prior art method of forming the landing pad 29 is performed on a semiconductor wafer 10, which employs a first photoresist layer 20 and a second photoresist layer 28 to define the positions of a contact plug 27 and the landing pad 29. As shown in FIG. 1, the semiconductor wafer 10 comprises a silicon substrate 12, a first dielectric layer 18 positioned on the silicon substrate 12, and a first photoresist layer 20 positioned on the first dielectric layer 18. Two gates 14, 16 are positioned on the silicon substrate 12, covered by the first dielectric layer 18, with a spacer 17 positioned on either side, respectively. The first photoresist layer 20 comprises an opening 22, extending down to the surface of the first dielectric layer 18, and positioned between the two gates 14, 16 for defining the position of the contact plug 27.
As shown in FIG. 2, an anisotropic etching process is performed to vertically remove the first dielectric layer 18 beneath the opening 22 to form a contact hole 24. Then, a stripping process is performed to remove the first photoresist layer 20 on the dielectric layer 18. Next, as shown in FIG. 3, a polysilicon layer 26 is formed on the semiconductor wafer 10 to fill the contact hole 24. Next, as shown in FIG. 4, a second photoresist layer 28 is formed on a predetermined area of the semiconductor wafer 10 above the contact hole 24 for defining the position of the landing pad 29.
Finally, as shown in FIG. 5, the polysilicon layer 26 not covered by the second photoresist layer 28 is removed and the residual polysilicon layer 26 becomes a conductive layer 26a. After the second photoresist layer 28 is removed, the landing pad 29 is completed. The top of the conductive layer 26a is used as the landing pad 29 and the bottom of the conductive layer 26a is used as the contact plug 27 for electrically connecting the landing pad 29 with a drain/source positioned under the silicon substrate 12.
Please refer to FIG. 6. FIG. 6 is a sectional schematic diagram of a capacitor formed on the landing pad 29 shown in FIG. 5. In DRAM processing, the surface of the semiconductor wafer 10 is usually defined and differentiated as both an array area 11 where the memory cells of the DRAM are formed, and a periphery area 13 where the periphery circuits are formed. After both the formation of the gates 14, 16 in the array area 11 and at least one gate 15 in the periphery area 13, the landing pad 29 and a capacitor are formed in the array area 11. Then, an interconnecting process is simultaneously performed in both the array area 11 and the periphery area 13 for electrically connecting the memory cell and the periphery circuits with the external circuitry.
According to the above-mentioned DRAM process, a second dielectric layer 30, a node contact 31, a bottom storage node 32, a third dielectric layer 33 and an upper field plate 34 are sequentially formed after the completion of the landing pad 29 in the array area 11. The bottom storage node 32, the third dielectric layer 33 and the upper field plate 34 together form a capacitor 39. One of the gates 14, 16, the contact plug 27, the landing pad 29 the node contact 31 and the capacitor 39 together form a memory cell 40.
Next, the interconnecting process is performed to form a fourth dielectric layer 35 on the semiconductor wafer 10 followed by an etching process. Therefore, a first groove (not shown) extending down to the upper field plate 34 is formed in the array area 11 as a channel for electrically connecting the memory cell with the external circuitry. Concurrently, a second groove 38 extending down to the silicon substrate 12 is formed in the periphery area 13 as another channel for electrically connecting the periphery circuits with the external circuitry.
In the prior art method, the lithographic process must be performed twice in the formation of the first photoresist layer 20 and the second photoresist layer 28 to define the position of the landing pad 29. Consequently, the result is a complicated process that is difficult to control. In addition, the sequentially-formed node contact 31 may electrically interact with a bit line (not shown) within the second dielectric layer 30 to cause product defect.
Furthermore, the landing pad 29 is formed on the first dielectric layer 18 and is electrically connected to the silicon substrate 12 with the contact plug 27 positioned within the first dielectric layer 18. Consequently, the thickness of the memory cell 40 subsequently formed in the array area 11 is very large. Therefore, the distance from the surface of the fourth dielectric layer 35 to the surface of the silicon substrate 12 is effectively great to cause difficulty in the formation of the second groove 38.
It is therefore a primary objective of the present invention to provide a method of automatically defining a landing via of a semiconductor wafer, and more particularly, a method of fabricating each landing pad on the source and drain of a MOS transistor without the use of a photoresist layer to define the position of the landing pad.
In a preferred embodiment of the present invention, the semiconductor wafer comprises a substrate and a conductive layer formed on the surface of the semiconductor wafer. The present invention involves first forming a photoresist layer on the surface of the conductive layer. Then patterns of a plurality of word lines are defined on the surface of the photoresist layer, and patterns of a plurality of auxiliaries are defined around the area predetermined to form the landing via between each two word lines on the surface of the photoresist layer. Thereafter, the patterned photoresist layer is used as a hard mask to etch the conductive layer to form each word line on the semiconductor wafer, and to simultaneously form the auxiliaries around the area predetermined to form the landing via. Finally, a plurality of spacers are formed around each word line and each auxiliary dovetail together to form a landing via hole and to automatically define the position of the landing via.
In the present invention, when defining patterns of each word line on the photoresist layer, patterns of a plurality of auxiliaries are simultaneously defined around the area predetermined to form the landing via between each two word lines on the surface of the photoresist layer. Thus, in the subsequent etching process of forming each word line, the auxiliaries are simultaneously formed around the area predetermined to form the landing via. Furthermore, a plurality of spacers formed around each word line and each auxiliary dovetail together to form a landing via hole and to automatically define the position of the landing via.
This and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after having read the following detailed description of the preferred embodiment which is illustrated in the various figures and drawings.